Recently, attention is paid to a Resistive Random Access Memory (ReRAM) which stores resistance value information, for example, a high resistance state and a low resistance state of an electrically rewritable variable resistive element in a non-volatile state as a non-volatile memory device. The ReRAM is configured such that, for example variable resistive type memory cells to each of which a variable resistive element as a memory element and a rectifying element such as a diode and the like are connected in series are disposed in an array state at intersecting points of plural word lines extending in parallel in a first direction and plural bit lines extending in parallel in a second direction vertical to the first direction (refer to, for example, US2009/0137112). Further, the non-volatile memory device having such a structure that plural memory cell arrays are stacked as well as a first wiring or a second wiring is shared between memory cell arrays which are adjacent in a stacked direction is also proposed (refer to, for example, US2009/0283739).
As described in US2009/0283739, the non-volatile memory device is manufactured as described below. A first wiring material layer acting as a word line and a first memory layer, which includes a variable resistive layer acting as a variable resistive element and a diode layer acting as a rectifying element, are stacked on an interlayer insulation film. Next, the first wiring material layer and the first memory layer are etched to line-and-space patterns extending in a first direction by a lithography technique and the reactive ion etching (hereinafter, called the RIE method), and an interlayer insulation film is embedded between the patterns. With the process, the first wiring material layer is made to a word line. Thereafter, a second wiring material layer acting as a bit line and a second memory layer, which includes a variable resistive layer and a diode layer, are stacked on the interlayer insulation film, the second memory layer, the second wiring material layer, the first memory layer, and the interlayer insulation film are etched to line-and-space patterns extending in a second direction by the lithography technique and the RIE method, and an interlayer insulation film is embedded between the patterns. With the process, a memory cell array of a first layer, in which the second wiring material layer is made to the bit line and memory cells having a columnar structure are disposed in a matrix state at cross points of word lines and bit lines, is formed.
Thereafter, memory cell arrays of plural layers are formed by repeatedly performing the same processes. Note that, when a memory layer of an uppermost layer is formed, it is sufficient that a wiring material layer, which acts as a word line or a bit line, is formed on the memory layer of the uppermost layer which is patterned in a first or second direction and in which an interlayer insulation film is embedded between the patterns, a wiring material layer and a memory layer just under the wiring material layer are processed to line-and-space patterns extending in the first or second direction by the lithography technique and the RIE method, and a portion between the patterns is embedded with an interlayer insulation film. When a stacked film of the wiring material layer and the memory layer is etched to the line-and-space patterns, the etching is ordinarily performed using a hard mask, which is composed of an oxide film such as a Tetraethoxysilane (TEOS) film and the like, on the stacked film as shown in US2009/0137112.
Incidentally, when plural memory cell arrays are stacked as in US2009/0283739, memory cells arrays for two layers are processed. At the time, however, an interlayer insulation film, which is composed of an oxide film embedded between the line-and-space patterns, must be also etched in addition that the memory layer and the wiring material layer are etched. That is, a problem arises in that a kind of films to be processed by the hard mask is increased.